This invention relates to photolithography, and, more particularly to a process for depositing, upon substrates, lines of a width of 0.5 micrometers or less.
Integrated circuits are arrays of microelectronic devices whose sizes are very small. In a typical integrated circuit, hundreds or even thousands of devices such as transistors, resistors, capacitors, etc. are deposited upon a single substrate and interlinked so as to perform selected functions. Integrated circuits are used in a wide variety of consumer, industrial, and military electronics. Their small size, with possibly thousands of individual devices in an area of one square inch, provides enormous computing power in a small, lightweight unit. The small size also reduces the power consumption and increases the operating and computing speed of the unit. Microelectronics and integrated circuits make possible the microcomputer and many other electronic advances.
Since the integrated circuit was first discovered, there has been a continuing search for methods to fabricated the circuits in ever smaller sizes. Reductions in size translate to increased operating speed, as well as greater computing power in a small area.
The conventional approach to fabricating integrated is in a layered configuration. Successive layers of metals, insulators, and semiconductors are deposited upon a substrate in carefully selected patterns to form devices, interlinked by metallic conductor paths to form arrays and, ultimately, the integrated circuit. Since the integrated circuit was first discovered, there has been a continuing search for methods to manufacture the circuit in ever-smaller sizes.
At the present time, most integrated circuits are fabricated by photolithography, which utilizes photoreduction together with sophisticated masking procedures to create particular configurations of the layers. In a typical photolithographic procedure, a layer of a photoresist material is deposited over a semiconductor layer. A solid mask having openings therethrough is placed over the photoresist layer. A portion of the photoresist layer is flood exposed through the openings in the mask using visible or ultraviolet light, causing a chemical change in the photoresist material. The photoresist material is then removed in the exposed regions (positive photoresist), leaving a pattern of semiconductor regions that are exposed and a corresponding pattern that is protected by the remaining photoresist material. With the semiconductor so patterned, the exposed regions can be removed by etching, or new material can be deposited into the exposed regions, as may be required. These procedures are then repeated as many times as necessary to build up a circuit with many devices thereon. In the course of fabricating a moderately complex integrated circuit, there may be dozens of such masking, patterning, and etching or depositing procedures. Manufacturing machines to perform these functions on a semi-automated basis are widely available in the microelectronics industry.
The ability to reduce the size of features in microelectronic devices is limited by the resolution that can be attained with these techniques. As the photographic reductions are increased, the features in the pattern become fuzzy and irregular in form, due to a combination of limitations in the deposition procedure and optical interference effects. Existing mass production patterning techniques are limited by a minimum resolution of several micrometers. (One micrometer is about 1/25 of one thousandth of an inch.) Advanced techniques under research allow minimum resolutions of about 0.8 mirometer. There are no optical projection techniques for attaining resolutions of 0.5 micrometers or less.
Resolutions below 0.5 micrometers can presently be attained by other approaches, such as electron beam patterning. Instead of using a mask and flood illumination of a resist layer with light, the pattern is written directly onto the surface of the resist by an electron beam operated under computer control to form the pattern. This approach requires that the features of the layer be patterned sequentially, one after the other, and is termed a "step and repeat" technique. It requires more costly and complex apparatus than now used.
By contrast, the approach described previously is a "flood illumination" technique, wherein all of the features are exposed simultaneously through the mask. The exposure is conventionally performed with a 10.times. stepper, which achieves high quality images by using a mask that is 10 times the size of the final image and reduction optics, and by precisely aligning, focusing, and exposing the pattern repeatedly over the wafer. The stepped flood illumination approach is generally preferred because of its greater speed and lower cost, but the electron beam approach must currently be used to attain feature resolutions of less than 0.5 micrometers.
There exists a need for a stepped flood illumination patterning technique that achieves resolutions of 0.5 micrometers and less through the use of ultraviolet light. Such a technique would permit significantly higher device packing densities and higher integrated circuit operating speeds than presently possible. Ideally, such a technique would utilize the same apparatus as now used for achieving resolutions of 1 micrometer and greater, so that the speed and cost advantages of existing stepped flood illumination procedures could be realized, without the need for new equipment investment. The present invention fulfills this need, and further provides related advantages.